The present invention relates to the field of memory controllers. More specifically, the present invention relates to a method and apparatus for arbitrating deferred read requests.
Revision 2.1 of the Peripheral Components Interconnect (PCI) Local Bus Specification, PCI Local Bus Rev. 2.1 effective Jun. 1, 1995, introduces the concept of deferred read cycles on the PCI bus. A memory read request is deferred when the request to access memory requires more than a predetermined period of time. After the predetermined period of time, the PCI master making the read request must relinquish the address and data lines to allow other PCI masters to access the memory. The memory controller instructs the PCI master making the read request to retry the read request at a later time.
Whether the PCI master is able to successfully access the memory within the predetermined period of time on its next retry depends on the traffic on the PCI bus and in the memory. If the PCI master is unable to access the memory within the predetermined period of time, the memory controller will again defer the memory read request and instruct the PCI master to retry the read request at a later time. Because the PCI master consumes PCI bus bandwidth each time it retries a read request, bandwidth that otherwise could be used to transfer data to other PCI devices is lost each time a retry is attempted and fails. In addition, the PCI master making the read request is required by the PCI Local Bus Specification to continue trying to access the memory until it is successful. The PCI master making the request is prevented from performing other tasks until it completes its read request. Thus, the requirements for deferring and completing read requests can produce inefficiencies that adversely affect the allocation of PCI bus bandwidth and the performance of PCI masters.
An apparatus according to a first embodiment of the present invention is disclosed. The apparatus includes a memory interface. The memory interface determines an access time of an original read request. The memory interface outputs a data ready signal when the access time of the original read request expires. An arbiter is coupled to the memory interface. The arbiter arbitrates access to the memory interface. A blocking unit is coupled to the memory interface. The blocking unit blocks a retry of the original read request from reaching the arbiter unit until the data ready signal is output by the memory interface. According to one embodiment of the memory controller a bus interface is coupled to the memory interface. The bus interface issues a deferred read signal to the device making the original read request upon receiving a signal from the arbiter.
An apparatus according to a second embodiment of the present invention is disclosed. The apparatus includes a memory interface. The memory interface determines an access time of an original read request. The memory interface outputs a deferred read signal when the access time is longer than a predetermined period of time. The memory interface outputs a data ready signal when the access time has expired. An arbiter is coupled to the memory interface. The arbiter arbitrates access to the memory interface. A blocking mechanism is coupled to the memory interface. The blocking mechanism outputs a request signal to an arbiter unit in response to receiving a retry read request signal from a device making the original read request and the data ready signal from the memory interface.
A method for arbitrating read requests to a memory according to a third embodiment of the present invention is disclosed. An access time of a read request is determined. The read request is blocked from being retried until the access time has expired. According to one embodiment of the present invention, a device making the read request is informed that the read request must be retried if the access time is greater than a predetermined period of time. According to an alternate embodiment of the present invention, the device making the read request is informed that the read request must be retried if the read request is made by the device for the first time.